Testable Chip Design Structure
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
One of the problems with large networks is that the sheer volume of associated data makes test generation/fault simulation an almost prohibitive task. Since a chip is the first physical entity to go through a test generation/testing process, what is needed to solve the above problem is a design structure where tests for the chip are guaranteed to be usable at higher package levels, irrespective of how its personality, as viewed from its inputs to its outputs, is changed by wiring on the higher package. Such a structure, described below, enables users of chip test data to test the chip and also simplifies the logic model for testing the module/card interconnection. To achieve the above, the circuitry surrounding drivers D and receivers R on a chip 1 must be in the form shown in Fig. 1.