Browse Prior Art Database

Microprocessor Interrupt Control

IP.com Disclosure Number: IPCOM000065141D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Rehage, TA Ripberger, R [+details]

Abstract

The selected microprocessor has the potential of operating on one of eight interrupt levels. The processor examines an "Interrupt Request" line at the end of each instruction cycle to see if an interrupt has occurred. If this line is active, the microprocessor will sample a three BIT encoded interrupt level (0-7) and initiate a level swap from the currently active level to the new requested level. The function of the interrupt hardware described below is to provide the interface between the various interrupts within the machine and the microprocessor interrupt inputs. The interrupt hardware will handle up to seven levels of interrupt and one background level. The seven interrupt lines are DC-sampled at the beginning of each cycle.