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PARTITIONING of PLA LOGIC Disclosure Number: IPCOM000065153D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Grice, D Killen, C Ng, T [+details]


A method is described for automatically deriving a physical partitioning of PLA logic into sub-parts, such as macros or "multi-master- slices". (A "master-slice" is a VLSI chip in intermediate form, completely laid out except for some piece of personalization, such as wiring. "Multi-master-slice" describes a situation where some large piece of logic cannot fit onto one master-slice, and so must be placed on two or more VLSI chips which are then wired together.) The method does not require the specification of the physical implementation by the logic designer.