ON-CHIP TESTER SIGNAL
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
Electronic Chip-In-Place Test (ECIPT) methodology requires that each chip on a higher level package have an ECIPT TESTER control input. This TESTER control is used to place the chip into "system" or "tester" mode independent of the mode of other chips on the package. Note: "system" refers to normal or expected chip operation, and "tester" refers to the operation of the chip as an extension of the tester.