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Implementation of Diagnostics and Redundancy on a Programmable Logic Array Disclosure Number: IPCOM000065172D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Colao, R Hsieh, JC Hsieh, YN Wu, WW [+details]


This invention provides diagnostics and redundancy on a very large- scale integration (VLSI) programmable logic array (PLA). A typical VLSI PLA is personalized with one mask level, namely, metal level only. In a typical layout, a cell is provided by way of an field-effect transistor (FET) device connecting appropriate lines in the array which may or may not be connected, depending upon the character of the array. The cell is personalized by connecting the gates of selected FET devices to the proper bit lines. Such VLSI PLAs are mass produced by stockpiling the wafers preprocessed up through a general metallization level. All of the array devices are metal connected to their associated lines to begin with. The array is personalized using a metal- deletion mask to delete unwanted lines.