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Error Correction for Memory Subsystems

IP.com Disclosure Number: IPCOM000065175D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Basilico, A Horton, R [+details]

Abstract

This article describes a system which can correct all single "hard" errors and 50% of all double errors in a memory subsystem. In addition, all single "soft" errors can be corrected. The invention does not rely on an Error Correcting Code (ECC). Rather, it can be used with a "parity-only" system. If desired, ECC can also be applied in connection with the invention to obtain additional error correction capability. A "shadow memory" is used; that is, a duplicate set of memory cells is provided which is simultaneously written with the same data written into the base set of memory cells. Each set of cells is divided into two parts, a High Byte part of 64K and a Low Byte part of 64K. The memory subsystem is hardwired so that code instructions can interchange the High Byte or Low Byte parts between shadow and base.