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L1 for Testable Logic Disclosure Number: IPCOM000065188D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Langston, DG [+details]


This simple decode checking logic allows minimized combinational logic circuits to be tested for stuck-at-zero faults, without the use of force error lines that are detrimental to the performance of the machine. The ability to allow this testing is provided by using an L1 (latch) in the checking logic, as shown in Fig. 3. Fig. 1 shows a simple example of minimized combinational logic for decode checking which has no allowance for checking a stuck-at-zero fault. Fig. 2 shows the current method of solving testability of such logic, using a separate signal to allow each decode checker to be tested. As shown in Fig.