Method of Reducing Stress in Semiconductor Chip Passivation
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
Integrated circuit chips develop high residual stresses in the top SiO2 passivation layer after putting on solder joints, especially when lead 95%-tin 5% is used as solder. The stresses are highest near the surface, in the immediate neighborhood surrounding the perimeter of the solder pad. A schematic structure of the chip including solder joint 1 is shown in the figure. In the approximate analysis, it can be shown that a high tensile stress of 3-5x109 dynes/cm2 (exceeding the tensile strength of the SiO2) is located in the top 1 mm layer 2 of SiO2 in the immediate neighborhood of the solder pad 1. The usual sputtered SiO2 on silicon substrate 3 exhibits an intrinsic compressive stress of about 1.5x109 dynes/cm2, uniformly distributed through the thickness (N10 mm) of the composite SiO2 layers 2, 4, and 5.