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High-Performance Clock Generation Supporting a High Degree of Testability Disclosure Number: IPCOM000065200D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Johnson, WM [+details]


The present system allows for testing of clock logic, and sequencing of clocks for hardware debugging. The present system supports a high degree of system test without any sacrifice of performance. Fig. 1 shows a diagram of the present system. The system includes a clock generation section and a supporting processor. The supporting processor attaches to the clock generation section, and is used for controlling and inspecting the system. The processor system is composed of a processor, storage controller, I/O (input/output) interface adapter, and storage interface adapter. Fig. 2 shows details of the clock generation and its attachment to the supporting processor. There are three major components in the clock generation, the clock generation logic, the clock output latches, and the clock deskew and damping circuits.