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Managing Resets in a Data Storage Hierarchy Disclosure Number: IPCOM000065211D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue


Related People

Berger, BH Booker, SK Smith, BP Wong, BB [+details]


Microcoded controls in a data storage hierarchy selectively delay resets for assuring data and subsystem integrity. Critical operations are identified. Such critical operations are not instituted unless such operations can be completed before receiving a reset. If a reset is received during the execution of a critical operation, the reset is deferred until completion of the critical operation. A plurality of host processors is connected through a peripheral control to a plurality of devices (not shown). Peripheral control, shown in the Overview Diagram, includes a reset timer which can time- out for "K" milliseconds (KMS). Identified critical modules invoke the reset control.