Browse Prior Art Database

Simulated Co-Processor ROS BIOS in System RAM Space

IP.com Disclosure Number: IPCOM000065225D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Buckland, PA Irwin, JW [+details]

Abstract

The present method provides space within a co-processor RAM (random- access memory) which cannot be accidentally destroyed by the co-processor program. Utilizing the method of the present invention when the co-processor is brought on line, the main processor loads the BIOS (basic input/output system) code into a section of RAM. This may be either RAM on the bus at the top of the first 1 megabyte of memory or memory in main storage with the Translation Control Words (TCWs) set to assign it in that address space. Hardware on the co-processor card monitors the address lines and suppresses the memory write signal when the address is in this range, thus making the range effectively ROS (read-only storage) space. Instructions can be fetched from the area, but no modification of the area by the co-processor is possible.