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Command Encoding for Programmable Logic Sequencers

IP.com Disclosure Number: IPCOM000065231D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Riley, MW Siegel, DW [+details]

Abstract

An arrangement is described in which the inputs and outputs of a Programmable Logic Sequencer (PLS) are maximized. This can simplify and cost reduce a design using PLS. PLS provides a mechanism for designing state machines in a single programmable chip. PLS devices in general have a larger number of inputs than outputs. For example, one commercially available PLS has sixteen inputs and eight outputs. The sixteen inputs to the PLS devices provide the designer access to a large amount of data to be used to make decisions in the sequencer. The outputs of the sequencer for certain applications can be insufficient. Based on the amount of input data available to the PLS, it is easy to design digital logic systems that require more outputs than available on the PLS.