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Chip-To-Substrate Bonding and Metallic Thermal Shunt

IP.com Disclosure Number: IPCOM000065237D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Durand, RD Yeh, C [+details]

Abstract

This article presents a method of solder bonding integrated circuit chips to ceramic substrates and a metallic thermal shunt that provides improved chip cooling. Chip-to-Substrate Bonding Bonding connector 5 (Fig. 1) connects the overhangs of a chip to the substrate. Connector 5 has three layers. The middle layer 10 is a solder-preform, such as 60/40 Pb/Su, sandwiched between two layers of seal-bands 11. The seal-band 11 compositions can be Mo/Mn + Ni+Au on the chip, and Mo+Ni+Au on the substrate. The width of connector 5 can be varied from chip to chip. Varying the seal-band thickness can accommodate variations in chip height. Seal bands are applied to both chip and substrate (Fig. 2), and solder-preform set between them. Total height (H) is the same for both connector 5 and the C4 pads before oven reflow.