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Combined LSSD and Logic Block

IP.com Disclosure Number: IPCOM000065241D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Griffin, WR Heller, LG [+details]

Abstract

A level sensitive scan design (LSSD) integrated with logic function is combined into one circuit block. The block, as indicated in the figure, includes a combinatorial logic network and it complements having data-in terminals and a pair of complementary output terminals QL1 and QL1 . Under normal operation, øTEST at the control gate of N channel transistor T1 is low turning off T1. When øDATA applied to transistor T2 is high, either the logic network or its complement conducts to pull down the voltage at output terminal QL1 or QL1, respectively. The logic network and its complement may be a complex logical function involving several inputs. The output terminals QL1 and QL1 are latched through P channel devices T3 and T4 in stage 1. Alternatively, N channel devices (not shown) may be used.