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Pseudo-Clocked Cascode Voltage Switch Logic System

IP.com Disclosure Number: IPCOM000065243D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Miersch, E Wagner, O [+details]

Abstract

This article describes a pseudo-clocked logic circuit comprising combinatorial cascode voltage switches (CVS trees) serially arranged in a chain between a sending and a receiving LSSD latch. The internal nodes of each tree of the chain are precharged before propagating logic information through the chain. An N-channel cascode voltage switch (CVS) tree (Fig. 1) is capable of providing any logic function conceivable with n inputs A, A to Z, Z (true/complement each) and two internal nodes N1 and N2 connected to true/complement outputs T and T via inverting buffers B1 and B2. The internal nodes N1 and N2 are connected to supply voltage +V through serially arranged P-channel precharge device pairs 1a, 1b and 2a, 2b, respectively. The precharge devices are controlled by a dominant (tree blocking) input pair A, A .