Browse Prior Art Database

Fast Pseudo-Clocked Cascode Voltage Switch Logic System

IP.com Disclosure Number: IPCOM000065244D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Blum, A Miersch, E Schulze-Schoelling, H Wagner, O [+details]

Abstract

Pseudo-clocked logic circuit comprising combinatorial cascode voltage switches (CVS trees) serially arranged in a chain between a sending and a receiving level sensitive scan design (LSSD) latch. The internal nodes of each tree of the chain are precharged before propagating logic information through the chain. Attention is drawn to the preceding article which describes the standard pseudo-clocked CVS logic system. A fast pseudo-clocked chain of n CVS trees in an LSSD environment is shown in Fig. 1. The principal feature of the chain consists in connecting the output pair T, T (true/complement) of each tree to a dominant input pair, say, A, A, of the respective next tree in the chain. The chain is arranged between a sending and a receiving LSSD latch latched by latch-up clocks C1 and C2, respectively.