CVS Load Circuit
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
A complementary metal oxide semiconductor (CMOS) single-ended cascode voltage switch (CVS) load circuit is provided which eliminates dual P channel networks and thus reduces the input capacitance and layout area. The circuit also provides power and delay improvements and allows efficient OR dotting for large variable expressions which may be processed in one functional block. The CMOS CVS circuit is illustrated in Fig. 1. This circuit includes an N channel combinational network having a plurality of inputs with a load circuit having two serially arranged P channel transistors T1 and T2 disposed between a voltage source VH and an output terminal Q, with T2 being disposed between T1 and terminal Q.