Customized Clock-Based Logic Design
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
This disclosure describes a design methodology that allows a subsystem of relatively lower performance capability to operate at the higher speed of the central system to which it is attached. The performance requirement is mandated by overall system performance while the subsystem capability is often limited by available technologies. The methodology calls for the use of multiple copies of an identical, but very precise, clock on the subsystem interface T0 which can be produced easily by the central system's clock network. Each of these clocks are assigned to individual performance-critical control lines on the subsystem interface where they are delayed once upon entry to the subsystem using precise delay lines (triangles in the figure).