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Reduction of the Area of a Microprocessor Chip Using the LSSD Chain in System Mode

IP.com Disclosure Number: IPCOM000065283D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Desrosiers, B Peter, JL Sitbon, C Steimle, A [+details]

Abstract

In a microprocessor performing dividing operations with a one-bit nonrestoring algorithm, a shift left is performed on the quotient register made of LSSD (Level Scan Sensitive Device) latches, using the latch chain normally devoted to the LSSD test. Using a one-bit non-restoring algorithm, one quotient bit is calculated starting from the high-order to the low-order bit of the two input numbers. Thus at each cycle, the quotient bit has to be latched in the quotient register and the previous quotient bit has to be shifted into the next left position of the quotient register.