Method of Communication of a High Speed Communication Adapter
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
This method is particularly adapted to give the best compromise for high speed full duplex data communication with minimum load on the processor bus. To allow high speed data transfer between the full duplex High Level Data Link Control (HDLC) line and the Unit Processor (UP) I/0 BUS, data exchange is performed by Direct Memory Access (DMA) between the HDLC module and intermediate buffer or by halfword cycle steal burst between the intermediate buffer and UP. These methods are usual for high speed data exchange. The particularity of the High Speed Adapter (HSA) lies in its way of handling cycle steal operations. To reduce the microprocessor interference, one cycle steal operation is completely defined by the exchange between UP and the HSA of one control block followed by the associated data block.