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Instruction Space Handling for Several Interrupt Levels

IP.com Disclosure Number: IPCOM000065289D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Blanc, A Jeanniot, P Spalmacin-Roma, S [+details]

Abstract

This article explains how to provide several interrupts on a single- interrupt-level microprocessor. Depending on the different causes of interrupt, which must be exclusive, (e.g., programmable I/0 operations coming from a unit processor) a hardware decode provides the highest memory address bits of the microprocessor instruction space, which replace the highest memory address bits of the microprocessor. The instruction space contains a non-interrupt zone and an interrupt zone which is divided into several interrupt routines. Each interrupt routine corresponds to one cause of interrupt.