Browse Prior Art Database

Extra Pads and Circuits in a Floating Point Unit to TEST the Embedded ARRAY

IP.com Disclosure Number: IPCOM000065291D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Desrosiers, B Peter, JL Sitbon, C Steimle, A [+details]

Abstract

In a floating point unit comprising an embedded RAM (random-access memory) array, extra pads and circuits are provided to allow the RAM array to be tested like a standard RAM. A direct access to the array reduces the test patterns used to test and evaluate their test performance. The extra gates connected to the extra pads are under control of the ARRAY TEST MODE pad. When this pad is activated, the write, read and address control signals are directly provided to the embedded memory by the extra pads and gates. When this pad is not selected, the other extra pads are inhibited. Thus in normal mode the read, write and address control signals are provided by the RANDOM LOGIC GATES under control of the microinstructions. A RESET pad is provided. This pad is inactive in normal mode.