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Shift Register Using Single Latch Per Stage

IP.com Disclosure Number: IPCOM000065299D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Tsui, F [+details]

Abstract

A shift register using only a single latch per stage can be designed for reliable shifting by distributing the shift control through a path parallel to the data-scan path, but in the opposite direction. For reliable latch operation, the width of the set-latch control pulse must the greater than the feedback-time tfb for the flip-flop to latch up. For latches in a shift register to use a common shift (set- latch) control, the width of the control pulse must be smaller than the sum of the feedthrough-time tft in the flip-flop and the delay dep in the external connection path, minus the skew in the control distribution. Normally, this latter condition is not naturally fulfilled, since, without special design for the control distribution, the skew can be large and comparable to dep .