Simple Wordline Boosting Circuit for High Performance CMOS DRAMS
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
This article describes a self-timed wordline boosting circuit that can be used in high-performance CMOS dynamic random-access memories (DRAMs). The proposed wordline circuit can be used to boost the selected wordline to more than a VT below the wordline volts during the writing, thereby avoiding the storage charge loss due to a PMOS threshold loss. A typical boost is to -2.0 V. The basic boosting circuit is shown in Fig. 1. [Signal XL (X-Line NOT) is locally generated and derived from the wordlines.] When one of the wordlines is pulled down by its decoder/driver circuit, the signal XL goes low. The signal (DOB+DOB) goes up when the data reaches the tri-state driver. XBL is the node to be boosted low, for example, to -2.0 volts. Referring to the waveform curves of Fig.