Browse Prior Art Database

Field-Effect Transistor

IP.com Disclosure Number: IPCOM000065309D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Kaplan, SB Speidell, JL [+details]

Abstract

A metal-insulator-semiconductor device can be made in the form of a comb-shaped array using sidewall processing. This structure can be used to induce a spatially varying potential at the semiconductor surface. After the source and drain are defined and the gate oxide, in the case of a Si-MOSFET, or the GaAs gate insulator layer is deposited, in the case of a GaAs-gate heterojunction, a vertical sidewall is fabricated near the source end of the channel. This is done by reactive ion etching photoresist or another suitable material. Then a sequence of depositions is done at an oblique angle to the wafer surface (N2Πto the vertical face of the wall, or N88Πfrom the normal vector of the wafer.