Single-Chip High-Speed Clock Recovery
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19
Phase-locked loops (PLLs) for clock recovery offer the best performance with reasonable design flexibility; however, PLLs are susceptible to false locking in the presence of spurious signals. This problem becomes more acute at higher frequencies and in single-chip designs where electromagnetic shielding is not possible. The described design minimizes spurious signals for an integrated high speed (400 MHz) clock recovery circuit. Phase-locked loops offer the best performance and design flexibility for clock recovery; however, a number of practical considerations limit their usefulness at high frequencies, especially in integrated form. Two major problems involve the lack of a stable high frequency voltage-controlled oscillator (VCO), and the propensity for PLLs to lock to spurious signals rather than the desired clock frequency.