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Dense Plate Control Sense Amplifier Circuit for Shared Word Line Random-Access Memories

IP.com Disclosure Number: IPCOM000065320D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

This shared word line dynamic random-access memory cell[*] sense amplifier (SA) features a dense layout, few devices and low SA overhead capacitance. The circuit shown in Fig.1 uses only 10 devices plus bit switches and four of the devices (multiplexing devices 2, 4, 2' and 4') lay out very compactly. Another advantage of this SA circuit is that the bit line does not go to the gate of any device other than the cross-coupled device, thereby minimizing SA overhead capacitance. The pulse program for operating the circuit is indicated in Fig.2. It should be noted that many devices in the circuit serve dual or triple purposes. For example, device 3 is used to discharge the plate line P1, charge the plate line back to Vdd, and precharge the bit line BL-- through the multiplexing device 2 from precharge (PC) line.