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Customized Metallization for Low Capacitance or Low Resistance

IP.com Disclosure Number: IPCOM000065322D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Cote, WJ Cronin, JE Scheuerlein, RE [+details]

Abstract

By means of a simple block mask and etch step method, multilayered metal interconnection lines can be customized for low capacitance or low resistance. The combination of this method and the electromigration resistance of the metals employed (Tungsten (W) + Titanium (Ti) Copper (Cu) in the multilayer structure permits higher line density than was previously possible. As shown in Fig. 1, a layer 2 to be contacted by wiring at a higher level has been overcoated with an insulating film layer 4. Via holes 6 are formed in the insulator 4, and wiring metallurgy is then deposited. First, the W plus a thin Ti layer are conformally deposited over the entire surface. Next, Cu lines are formed above the Ti by either an etching or a lift-off technique to complete the structure of Fig. 1.