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Overlap of Store Multiple Operation With Succeeding Operations Through Second Set of General Purpose Registers Disclosure Number: IPCOM000065325D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Emma, PG Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]


In known high-end processors, the parallel execution of operations subsequent to a store multiple instruction was halted due to the following reasons: 1. Subsequent fetches or stores may have conflicted logically with the stores in store multiple. 2. The bandwidth of the cache was highly utilized during execution of store multiple, and successive operations would have to wait on this facility. 3. The contents of the general-purpose registers (GPRs) could not be changed until the store multiple has stored their contents. Points 1 and 2 are not addressed in this article. Point 3 is the subject discussed here. For each GPR there will be a second GPR which is loaded exclusively from the first GPR.