Browse Prior Art Database

Alignment Fixture

IP.com Disclosure Number: IPCOM000065327D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Ledermann, PG Moskowitz, PA [+details]

Abstract

Concurrent formation of circuit leads and alignment holes on chip carriers permits greater placement accuracy and lead density. The alignment holes enable automated handling. Referring to the figure, flexible leaded chip carrier 1 has circuit lines 2 and alignment holes 3 formed by photolithographic and etching techniques. Carrier 1 is picked and placed by pins 5 which are part of knife-edge thermode assembly 4. The tapered alignment pins 5 enter holes 3 and position the carrier. As thermode 4 is lowered toward board 6, alignment pins 5 enter corresponding board alignment openings 7. The thermode, which contains a heating element, reflows the solder on the board 6 to attach the outer lead bonds. This process mechanically aligns board and carrier within closer tolerances and with less expense than using optical alignment.