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Multiplexed Address Selection Circuitry With Minimum Row-To-Column Delay Disclosure Number: IPCOM000065332D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

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Related People

Kalter, HL Nguyen, Q Patton, CS van der Hoeven, WB [+details]


This article describes address selection circuitry for a semiconductor memory which minimizes the row-to-column address delay for a multiplexed external and internal address bus system while reducing the address generator standby power, active power consumption and internal chip noise. The address selection circuitry for this design provides for multiplexed external and internal address busses using dual input address buffers and drivers and the output row drivers have tristate capability and dotted output lines. In the figure, an external memory storage address buffer (not shown) feeds input Ai. The input is sequentially latched into separate row and column address input buffers 1 and 2 which steer separate row and column address drivers 3 and 4 onto a shared internal true/complement address bus ai and ai.