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Anticipatory TARGET Assimilation for the EX Instruction

IP.com Disclosure Number: IPCOM000065334D
Original Publication Date: 1985-Nov-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Emma, PG Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

A Least Recently Used (LRU) stack that contains targets of Execute (EX) instructions is proposed. Rather than perform target fetch via a Branch History Table (BHT) mechanism, the Execute address is used to obtain the actual target instruction from this stack. This renders the timeliness of the actual target fetch unimportant, and it preserves the efficiency of normal BHT activity. The EX instruction generates a target address that designates an instruction that is to be executed. The target instruction is fetched, and the second byte of the target instruction is ORed with the lower byte of a General-Purpose Register (GPR) that is specified by the EX instruction. The target instruction, thus assimilated, is decoded and executed.