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Simultaneous Multiple-Address Space Feature Disclosure Number: IPCOM000065346D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

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Bischoff, G Capron, P Lucash, J Sangaline, E Stockwell, D [+details]


This method of memory implementation expands the addressing capability of an 8088/8086 processor by creating additional address lines that can access large blocks of memory. The operation is transparent to the application software. The memory control logic generates addresses which point to certain areas of a large memory bank based on an identifying (ID) word written by a control program. To switch between active memory areas, the control program writes a different ID word. A translate table must be initialized by a control program before the memory can be loaded. This memory control method extends the number of address lines generated by a processor and effectively adds additional address lines which can be used to address a block of memory larger than the processor is capable of normally addressing.