Data Separator Time Delay Circuit
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19
Digital data separators, which are phase-locked-loop based, must generate an error signal proportional to the time a data bit arrives early or late, as compared to a data window, while suppressing generation of an error signal when no data bit occurs. To determine whether a bit did not occur, or was just late, a time delay equal to one-half of the data window is usually generated. In MFM and run length 2,X codes (where "X" equals a number such as "7"), no two data pulses can occur on adjacent clock pulses. This circuit uses the extra clock pulse 10 (i.e., the clock pulse during which a data pulse cannot occur) to charge (11) a capacitor 12 for the duration of clock pulse 10, then discharge (13) capacitor 12 at the same rate upon the arrival of a data pulse 14.