Low Inductance Decoupling Capacitor Connection
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19
As the number of I/O's on LSI (large-scale integrated) and VLSI (very large-scale integrated) chips increase the wiring in the chip carrier (module) increases, thereby requiring additional wiring layers. As a result, the power connections to the chip lengthen, increasing inductance. This article places a capacitor on the module at each corner of the chip with a low inductance path provided by metal layers in the module strategically located close to the surface. This design requires signal fan-out connections on the surface of the module to allow for the uppermost internal layers to be dedicated to the capacitor- to-chip power connections.