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Diode-Etched Resistor Process

IP.com Disclosure Number: IPCOM000065366D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Cavanagh, RA Forneris, JL Travis, KJ [+details]

Abstract

The current resistor implant process utilized on bipolar integrated circuits contains two photolithographic masking operations: the implant itself, and a low temperature (900ŒC) anneal that is performed after all the transistor elements have been formed. The first masking step is executed for the purpose of field oxide removal and is done after the formation of the transistor base. The second masking operation does not involve dielectric etching; its only purpose is to serve as an implant mask. For this reason, the resist is 1800 A thick, as opposed to a normal thickness of 13500 A . The implant immediately follows with a boron dose and energy of 2.0E13 and 150 KeV, respectively, through a dielectric screen of 800 A of SiO2 under 1600 A of Si3N4 .