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TTL Data Latch With Symmetric Input Ports

IP.com Disclosure Number: IPCOM000065384D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article addresses a technique for increasing the number of I/O ports available to a common TTL (transistor-transistor logic) data latch while limiting impact on the basic cell layout to a minimum. A data latch having utility in TTL circuitry is shown in Fig. 1. It can be fabricated within the area of one TTL logic cell and is complete with separate ingate and outgate controls. Many applications, however, require more than one input port, and this need is met by the two-input-port data latch shown in Fig. 2. Since in Fig. 1 the T2 emitter needs to be wired to ground, the data ingate logic on the left side can be used on the right with no extra global wiring, i.e., the operation of input (write) port 2 is similar to that of input (write) port 1.