Improved Technique to Misalign Faults in a Fault-Tolerant Memory
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19
This disclosure describes new switching logic which provides much "richer" permutation capability with no increase in the number of gates, no increase in access time to the memory and a relatively small increase in register space to hold the larger permute vector which controls the switching matrix. This new logic will permit the scattering of bad bits in a fault-tolerant memory in a great many different ways with no increase in delay over other methods. The increase in size of the permute vector is "tunable" by the designer, such that he can trade off richness of permutation for decreased register space, if desired.