MTL Array With Refresh
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19
Complex circuits used to perform the discharge/restore processes essential to the function of a merged transistor logic (MTL) cell may be eliminated with benefit to array performance and stability by means of the organization disclosed in this article. Fig. 1 illustrates an MTL cell utilizing bit lines 'BL0' and 'BL1' and word line 'WL'. Transistors T2 and T4 serve as current injectors to the cell during standby and as 'read' and 'write' transistors during access. Unselected bits of the whole chip must be discharged for 'read/write' so that the selected 'drain line' can be activated to a 'low level'. All bit lines must be restored to the 'standby' level following access, a process necessitating the use of added complex circuits which, in turn, contribute to chip access and cycle delay. Fig.