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System Architecture for Efficient PIPELINE Execution of List-Directed Repetitive Processes and General-Purpose Emulation

IP.com Disclosure Number: IPCOM000065412D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Kriz, TA [+details]

Abstract

Computer arithmetic pipeline technology can be commonly found in both existing array processor products and "super-computer" products currently under development. In the array processor area, pipeline technology is typically limited by the nature of its architecture and structure to only supporting efficient execution of special language programs involving computation-intensive processes on vector operands composed of elements selected from an ordered sequence of memory locations. The software employed makes use of special system calls to an executive which initiates pipeline execution only of processes for which special micro-code routines have been pre-fabricated. The processes are typically restricted to a limited function set and, frequently, a single arithmetic type in terms of operand format and precision.