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Distributed Redundancy Schemes for Memory Arrays

IP.com Disclosure Number: IPCOM000065430D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

Word or bit redundancy schemes are employed on memory array products to obtain better yields in VLSI (very large-scale integrated) designs. This article concerns the improvements that can be obtained from distributing redundancy in smaller portions all over an array chip, thereby reducing the probability of total chip failure due to contiguous fails. In memory array products using either word or bit redundancy, the whole cell array is divided into a few contiguous portions, where one portion may be found defective. Available manufacturing data indicates that in a partially good chip, the defects of the bad portion are predominately due to single cell failures. For example, in a partially good chip of 4K x 9 (10), a whole portion of 4K cells is not used even though only a few are determined to be defective.