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Substrate Contact Through a Trench

IP.com Disclosure Number: IPCOM000065449D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Bergeron, DL Bergeron, RJ Chesebro, DG Trumpp, H [+details]

Abstract

A process is provided for electrically contacting a semiconductor substrate from the upper surface of a chip oar wafer without the use of any critical masking steps. As indicated in Fig. 1, a P type silicon substrate 10 has an N type epitaxial layer 12 grown thereon with an N+ subcollector region 14 formed at the junction thereof. An N+ reach-through region 16 extends from the surface of epitaxial layer 12 to subcollector region 14. A trench 18 is formed through a layer of silicon dioxide 20 and a layer of silicon nitride 22 and through epitaxial layer 12 and subcollector region 14 into substrate 10 by known reactive ion etching (RIE) techniques. A boron implant may be used to form channel stop region 24 at the bottom of trench 18.