Browse Prior Art Database

Restore Scheme With Reduced Bit Line Offset Voltage

IP.com Disclosure Number: IPCOM000065460D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Klein, W Klink, E Wernicke, FC [+details]

Abstract

A restore scheme with reduced bit line offset voltage is proposed wherein the bit reference line of the memory is connected to a current source accommodating the full base current. In bipolar semiconductor memories, currents of significantly different magnitude may flow in the left and the right bit line of an associated bit line pair, depending upon the bit pattern written in the cells, if a "1" or "0" is simultaneously stored in all cells. These different saturation voltages VCE-sat at the bit line switches TBS lead to a voltage difference (bit line offset voltage) between the two bit lines B0 and B1 and thus to noticeably increased access times during reading and reduced cell stability.