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Tunable Delay Line for Multilayer Ceramic Packages

IP.com Disclosure Number: IPCOM000065464D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Bartley, GK Johnson, CL [+details]

Abstract

A segmented delay line is imbedded in a multilayer ceramic package with top surface links. The imbedded delay line segments allow for widely varying delay line characteristics without significant impact on the surface area required. By cutting the top surface links, the total amount of delay in the circuit can be fine tuned. Fig. 1 represents a segmented delay line. Any number of delay segments D with cuttable links can be wired together, as shown. With all of the cuttable links intact, the total delay is essentially zero. Each time a cuttable link is severed, the total delay is increased by one delay segment D. Any number of the cuttable links may be severed at any of the delay segment locations; they do not need to be cut in a sequential pattern.