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Read-Only Memory With Inverted Data Bits

IP.com Disclosure Number: IPCOM000065469D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Nishihara, M [+details]

Abstract

In a read-only memory (ROM) using field-effect transistors (FETs), a word line delay time depends on a word line capacitance, in other words, how many data bits along the word line are programmed with cells having a thin oxide. If a cell having a thin gate oxide is defined as a data bit 1, a word line with many 1's will require a longer time to propagate data. If the personalization data is inverted from 1 to 0 or from a thin oxide to a thick oxide, the word line delay time will be greatly reduced. The original data can be obtained by inverting again the output of sense amplifiers depending on whether the personalization data along word lines were inverted or not. Fig. 1 is a sample of a ROM circuit, and Fig. 2 shows a bit information table for the word line WL1 and the word line WL2.