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Memory Address Translation Disclosure Number: IPCOM000065473D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

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Matsubara, S [+details]


This article describes a memory address translation wherein a main memory is checked if it includes a defective memory block, if the defective memory block is found, a block address part of the defective memory block is inverted and stored in a register, and during the memory access operations, a block address part of the address supplied from a microprocessor unit is Exclusively ORed with the inverted block address. This results an alternative memory block being accessed instead of the defective memory block. Referring to the figure, a 256K-byte main memory 1 is divided into 256 memory blocks and the highest block, which has a value '11111111' as an address A17 - A10, is reserved as an alternative memory block. An address for accessing the memory 1 is also shown in the figure.