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Data Correction System

IP.com Disclosure Number: IPCOM000065491D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Inomata, T Nagasaki, S [+details]

Abstract

This article describes a data correction system wherein a memory for storing data is divided into plural memory blocks, a map register is provided each bit position of which is assigned to each memory block and the bit position stores a binary data "1", which represents the existence of fixed data in corresponding memory block, and a table memory stores check sums for the fixed data in the memory block. In the figure, a random-access memory 1 is divided into plural 4K-byte memory blocks, for example, 1A through 1D. It is assumed that, in an initial program load operation, variable data, which are dynamically changed during the data processing, are stored in the 4K-byte memory blocks 1A and 1D, and fixed data, which are not changed during the data processing, are stored in the 4K-byte memory blocks 1B and 1C.