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Set-Dominant Set-Reset LSSD Transfer Gate Cmos Latch

IP.com Disclosure Number: IPCOM000065506D
Original Publication Date: 1985-Dec-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Aipperspach, AG [+details]

Abstract

Figs. 1 and 2 show two implementations of a set-dominant set-reset LSSD (level-sensitive scan design) latch. Both configurations work on the principle that Set input SO gates Reset input RO when Set is in a high state. During a CO clock cycle when CO is high, the value of node C determines the state of the L1 latch.