Divide by Three Asymmetric Counter Utilizing Two Flip-flops
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-19
A clock frequency supplied to line 10 is divided by three and delivered on line 11 through the interconnection of two D flip- flops 12 and 13. Input clock pulse train 10 is connected to the CK connections of both flip-flops 12 and 13. The Q connection of flip-flop 12 is connected by line 14 to the preset connection of flip-flop 13. The Q connection of flip-flop 13 is connected by line 15 to the D connection of flip-flop 12. The D connection of flip-flop 13 is grounded. The CL connection of both flip-flops 12 and 13 are connected to reset line 16. The preset connection of flip-flop 12 is connected to +5V.