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The RC component of the bitline is significantly reduced and the access and cycle time of the memory are directly improved by the contact between the polycide line and the N SKIN diffusion.
English (United States)
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Enhanced One Device Cell Containing Polycide N Skin Bitline Without Self-
The RC component of the bitline is significantly reduced and the access and
cycle time of the memory are directly improved by the contact between the
polycide line and the N SKIN diffusion.
The enhanced one device memory cell shown in Fig. 1 consists of storage
oxide 11 etched to define over a bitline area. The N SKIN implant 13 is
performed as in a standard process and a polycide line 14 is disposed over the N
SKIN 13 implanted into the silicon substrate 15 to form the bitline 12.
Any self-alignment requirement is eliminated by biasing the polycide line 14
toward the thick oxide boundary 18 as shown in Fig. 2. This is done during cell
layout by assigning point A a value such that a three sigma worst case shift
toward the word device 17 results in the minimum channel length allowed, i.e.,
point A will coincide with point C.
A three sigma shift in the opposite direction will result in the polycide line 14
running over the ROX 18, which is of no significance since point B will coincide
with point D. An increase in minimum Leff has minor (<10%) cell area impact.